https://libeldoc.bsuir.by/handle/123456789/37990| Title: | FPGA Based Arbiter Physical Unclonable Function Implementation with Reduced Hardware Overhead |
| Authors: | Ivaniuk, A. A. Zalivaka, S. S. |
| Keywords: | публикации ученых;Physical Unclonable Function;Arbite;FPGA;LUT;Symmetrical path |
| Issue Date: | 2019 |
| Publisher: | Springer |
| Citation: | Ivaniuk, A. A. FPGA Based Arbit Physical Unclonable Function Implementation with Reduced Hardware Overhead / Alexander A. Ivaniuk, Siarhei S. Zalivaka // Communications in Computer and Information Science book series. – 2019. – № 1055. – С. 216–227. – DOI: https://doi.org/10.1007/978-3-030-35430-5_18. |
| Abstract: | The paper presents a new architecture of symmetric paths of the arbiter PUF, providing efficient use of the hardware resources of LUT blocks for various Xilinx Artix-7 FPGA family. |
| URI: | https://libeldoc.bsuir.by/handle/123456789/37990 |
| Appears in Collections: | Публикации в зарубежных изданиях |
| File | Description | Size | Format | |
|---|---|---|---|---|
| Ivaniuk_FPGA.pdf | 751.96 kB | Adobe PDF | View/Open |
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