https://libeldoc.bsuir.by/handle/123456789/53912| Title: | RISC-V hardware modification for M-sequences generation |
| Authors: | Petrovsky, D. Ivaniuk, A. |
| Keywords: | материалы конференций;hardware modification;RISC-V architecture |
| Issue Date: | 2023 |
| Publisher: | БГУИР |
| Citation: | Petrovsky, D. RISC-V hardware modification for M-sequences generation / D. Petrovsky, A. Ivaniuk // Информационные технологии и системы 2023 (ИТС 2023) = Information Technologies and Systems 2023 (ITS 2023) : материалы Международной научной конференции, Минск, 22 ноября 2023 / Белорусский государственный университет информатики и радиоэлектроники ; редкол.: Л. Ю. Шилин [и др.]. – Минск : БГУИР, 2023. – С. 127–128. |
| Abstract: | A hardware modification of the soft processor core of the open RISC-V architecture to accelerate the generation of M-sequences is being considered. The results of a comparative analysis of the performance of completely software algorithms and an algorithm with support for hardware modification are shown, and the hardware costs for implementation in a Xilinx-7 FPGA chip are calculated. |
| URI: | https://libeldoc.bsuir.by/handle/123456789/53912 |
| Appears in Collections: | ИТС 2023 |
| File | Description | Size | Format | |
|---|---|---|---|---|
| Petrovsky_ RISC-V.pdf | 414.11 kB | Adobe PDF | View/Open |
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