https://libeldoc.bsuir.by/handle/123456789/41687| Title: | High performance multiplier-less pipelined FPGA architecture for 2-D non-separable quaternionic filter banks |
| Authors: | Rybenkov, E. V. Petrovsky, N. A. |
| Keywords: | публикации ученых;quaternionic paraunitary filter;non-separable transform |
| Issue Date: | 2020 |
| Publisher: | Poznan University of Technology |
| Citation: | Rybenkov, E. V. High performance multiplier-less pipelined FPGA architecture for 2-D non-separable quaternionic filter banks / E. V. Rybenkov, N. A. Petrovsky // Signal Processing: Algorithms, Architectures, Arrangements, and Applications : the 24th signal processing conference, Poznan, 23–25 september 2020 / Poznan University of Technology. – Poznan, 2020. – P. 42–47. – DOI: 10.23919/SPA50552.2020.9241273. |
| Abstract: | This paper presents a systematic design of the 2-D non-separable quaternionic paraunitary filter banks (Q−PUFB) based on the integer-to-integer invertible quaternionic multiplier applied to image processing. |
| URI: | https://libeldoc.bsuir.by/handle/123456789/41687 |
| Appears in Collections: | Публикации в зарубежных изданиях |
| File | Description | Size | Format | |
|---|---|---|---|---|
| Rybenkov_High.pdf | 44.88 kB | Adobe PDF | View/Open |
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