| Поле DC | Значение | Язык |
|---|
| dc.contributor.author | Petrovsky, N. | - |
| dc.contributor.author | Stankevich, A. | - |
| dc.contributor.author | Petrovsky, A. | - |
| dc.date.accessioned | 2016-12-20T12:38:29Z | - |
| dc.date.accessioned | 2017-07-27T12:23:23Z | - |
| dc.date.available | 2016-12-20T12:38:29Z | - |
| dc.date.available | 2017-07-27T12:23:23Z | - |
| dc.date.issued | 2015 | - |
| dc.identifier.citation | Petrovsky, N. Design and high-performance hardware architecture for image coding using block-lifting-based quaternionic paraunitary filter banks / N. Petrovsky, A. Stankevich, A. Petrovsky // 4th Mediterranean Conference on Embedded Computing (MECO), Budva, Montenegro, 14-18 June, 2015. – Budva, 2015. – P. 193–198. | ru_RU |
| dc.identifier.uri | https://libeldoc.bsuir.by/handle/123456789/10932 | - |
| dc.description.abstract | In this paper, we have introduced a generalized block-lifting structure using the 2-D CORDIC algorithm as a block of 4-band linear phase paraunitary filter banks (LP PUFB) based on the quaternionic algebra (Q-PUFB) for the lossy-to-lossless image coding. A bank Q-PUFB based on the 2-D CORDIC block-lifting structure reduces the number of rounding operations and has a regular layout. Since the block-lifting structures with rounding operations can implement the integer-to-integer transform (Q-PUFB). The parallel-pipelined efficient architecture (P2E_Q-PUFB) has been proposed. The low latency separable image processing is implemented in the given architecture. | ru_RU |
| dc.language.iso | en | ru_RU |
| dc.subject | публикации ученых | ru_RU |
| dc.title | Design and high-performance hardware architecture for image coding using block-lifting-based quaternionic paraunitary filter banks | ru_RU |
| dc.type | Article | ru_RU |
| dc.identifier.DOI | http://doi.org/10.1109/MECO.2015.7181901 | - |
| Располагается в коллекциях: | Публикации в зарубежных изданиях
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