| DC Field | Value | Language |
|---|
| dc.contributor.author | Zalivako, S. S. | - |
| dc.contributor.author | Ivaniuk, A. A. | - |
| dc.contributor.author | Chang, C. H. | - |
| dc.date.accessioned | 2018-12-04T13:13:00Z | - |
| dc.date.available | 2018-12-04T13:13:00Z | - |
| dc.date.issued | 2019 | - |
| dc.identifier.citation | Zalivaka, S. S. Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response / S. S. Zalivaka, A. A. Ivaniuk, C. H. Chang // IEEE Transactions on Information Forensics and Security. – 2019. – №4(14). – P. 1109 – 1123. - DOI : 10.1109/TIFS.2018.2870835. | ru_RU |
| dc.identifier.uri | https://libeldoc.bsuir.by/handle/123456789/33699 | - |
| dc.description.abstract | Field programmable gate array (FPGA) is a potential hotbed for malicious and counterfeit hardware infiltration. Arbiter-based physical unclonable function (A-PUF) has been widely regarded as a suitable lightweight security primitive for FPGA bitstream encryption and device authentication. Unfortunately, the metastability of flip-flop gives rise to poor A-PUF reliability in FPGA implementation. Its linear additive path delays are also vulnerable to modeling attacks. | ru_RU |
| dc.language.iso | en | ru_RU |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | ru_RU |
| dc.subject | публикации ученых | ru_RU |
| dc.subject | Arbiter PUF | ru_RU |
| dc.subject | reliability enhancement | ru_RU |
| dc.subject | machine learning attack resistance | ru_RU |
| dc.subject | authentication protocol | ru_RU |
| dc.title | Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response | ru_RU |
| dc.type | Статья | ru_RU |
| Appears in Collections: | Публикации в зарубежных изданиях
|
