| DC Field | Value | Language |
|---|
| dc.contributor.author | Zolotorevich, L. A. | - |
| dc.date.accessioned | 2019-10-08T09:11:58Z | - |
| dc.date.available | 2019-10-08T09:11:58Z | - |
| dc.date.issued | 2013 | - |
| dc.identifier.citation | Zolotorevich, L. A. Project verification and construction of superchip tests at the RTL level / L. A. Zolotorevich // Automation and Remote Control. – 2013. – Vol. 74, Issue 1. – PP. 113 – 122. – DOI: 10.1134/S0005117913010104. | ru_RU |
| dc.identifier.uri | https://libeldoc.bsuir.by/handle/123456789/36689 | - |
| dc.description.abstract | Methods were proposed for project verification and directed design of the superchip
tests represented in VHDL at the RTL level. The problem of test design and project verification
was solved on the basis of the CNF-satisfiability of some system of Boolean functions. | ru_RU |
| dc.language.iso | en | ru_RU |
| dc.publisher | Pleiades Publishing | ru_RU |
| dc.subject | публикации ученых | ru_RU |
| dc.subject | Remote Control | ru_RU |
| dc.subject | Boolean Function | ru_RU |
| dc.subject | Test Design | ru_RU |
| dc.subject | Program Code | ru_RU |
| dc.subject | Permission Function | ru_RU |
| dc.title | Project verification and construction of superchip tests at the RTL level | ru_RU |
| dc.type | Статья | ru_RU |
| Appears in Collections: | Публикации в зарубежных изданиях
|
