| DC Field | Value | Language |
|---|
| dc.contributor.author | Ivaniuk, A. A. | - |
| dc.contributor.author | Zalivaka, S. S. | - |
| dc.date.accessioned | 2019-12-27T11:27:30Z | - |
| dc.date.available | 2019-12-27T11:27:30Z | - |
| dc.date.issued | 2019 | - |
| dc.identifier.citation | Ivaniuk, A. A. FPGA Based Arbit Physical Unclonable Function Implementation with Reduced Hardware Overhead / Alexander A. Ivaniuk, Siarhei S. Zalivaka // Communications in Computer and Information Science book series. – 2019. – № 1055. – С. 216–227. – DOI: https://doi.org/10.1007/978-3-030-35430-5_18. | ru_RU |
| dc.identifier.uri | https://libeldoc.bsuir.by/handle/123456789/37990 | - |
| dc.description.abstract | The paper presents a new architecture of symmetric paths of the arbiter PUF, providing efficient use of the hardware resources of LUT blocks for various Xilinx Artix-7 FPGA family. | ru_RU |
| dc.language.iso | en | ru_RU |
| dc.publisher | Springer | ru_RU |
| dc.subject | публикации ученых | ru_RU |
| dc.subject | Physical Unclonable Function | ru_RU |
| dc.subject | Arbite | ru_RU |
| dc.subject | FPGA | ru_RU |
| dc.subject | LUT | ru_RU |
| dc.subject | Symmetrical path | ru_RU |
| dc.title | FPGA Based Arbiter Physical Unclonable Function Implementation with Reduced Hardware Overhead | ru_RU |
| dc.type | Статья | ru_RU |
| Appears in Collections: | Публикации в зарубежных изданиях
|
