| DC Field | Value | Language |
|---|
| dc.contributor.author | Petrovsky, D. | - |
| dc.contributor.author | Ivaniuk, A. | - |
| dc.coverage.spatial | Минск | en_US |
| dc.date.accessioned | 2023-12-20T06:36:31Z | - |
| dc.date.available | 2023-12-20T06:36:31Z | - |
| dc.date.issued | 2023 | - |
| dc.identifier.citation | Petrovsky, D. RISC-V hardware modification for M-sequences generation / D. Petrovsky, A. Ivaniuk // Информационные технологии и системы 2023 (ИТС 2023) = Information Technologies and Systems 2023 (ITS 2023) : материалы Международной научной конференции, Минск, 22 ноября 2023 / Белорусский государственный университет информатики и радиоэлектроники ; редкол.: Л. Ю. Шилин [и др.]. – Минск : БГУИР, 2023. – С. 127–128. | en_US |
| dc.identifier.uri | https://libeldoc.bsuir.by/handle/123456789/53912 | - |
| dc.description.abstract | A hardware modification of the soft processor core of the open RISC-V architecture to accelerate the generation of M-sequences is being considered. The results of a comparative analysis of the performance of completely software algorithms and an algorithm with support for hardware modification are shown, and the hardware costs for implementation in a Xilinx-7 FPGA chip are calculated. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | БГУИР | en_US |
| dc.subject | материалы конференций | en_US |
| dc.subject | hardware modification | en_US |
| dc.subject | RISC-V architecture | en_US |
| dc.title | RISC-V hardware modification for M-sequences generation | en_US |
| dc.type | Article | en_US |
| Appears in Collections: | ИТС 2023
|
