|Title:||Design and implementation of reversible integer quaternionic paraunitary filter banks on adder-based distributed arithmetic|
|Authors:||Petrovsky, N. A.|
Rybenkov, E. V.
Petrovsky, A. A.
|Keywords:||публикации ученых;quaternion;filter bank;L2L image coding|
|Citation:||Petrovsky, N. A. Design and implementation of reversible integer quaternionic paraunitary filter banks on adder-based distributed arithmetic / N. A. Petrovsky, E. V. Rybenkov, A. A. Petrovsky // Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA’2017): Proc. 21st Int. Conf., Poznan, Poland, September 20-22, 2017 / Poznan University of Technology. – Poznan : IEEE, 2017. – P. 17 - 22.|
|Abstract:||This paper presents a design method of reversible integer quaternionic paraunitary filter banks (Int-Q-PUFB) using the adder-based distributed arithmetic (DAΣ) for implementation multiplier block-lifting structure modules. The proposed quaternion multiplier (Q-MUL) and 8-channel Int-Q-PUFB processors are implemented on the FPGA Xilinx Zynq 7010. The total magnitude response of analysis-synthesis system based on the given Int-Q-PUFB shows that the 8-channel 8 × 24 Int-Q-PUFB is perfect reconstruction filter bank for finite precision. Compared to known solutions of Int-Q-PUFB using block-lifting structure based on the CORDIC devices and ROM-based distributed arithmetic the given DAΣ-based Int-Q-PUFB have more less implementation complexity and latency.|
|Appears in Collections:||Публикации в зарубежных изданиях|
|Petrovsky_Design.pdf||130.94 kB||Adobe PDF||View/Open|
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