Constant Multiplication Based on Boolean Minimization

Abstract

This contribution studies constant multiplication X ·C and X · C (mod P), where constant C achieves 2263 bits and variable X varies up to 10 bits. We aim to develop an efficient approach to design constant multiplication for FPGA and ASIC. The proposed technique demonstrates up to 2 times advantage in performance and up to 5 times advantage in area costs under direct multiplication on FPGA, up to 7 times in performance in custom library on ASIC.