Graph-Based Recognition of High-Level Structures in Transistor Circuits

Abstract

The problem of converting a flat transistor circuit into a hierarchical circuit of logical gatesis considered. The problem arises in layout versus schematic verification and reverse engineering of integrated circuits. The offered subcircuit recognition algorithm collects transistors into gates without using any predefined cell library. Graph-based methods are proposed for solving some key problems of subcircuit (CMOS gates) recognizing and logical network extraction. The presented graph methods have been implemented in C++ as a part of a decompilation program, which was tested using practical transistorlevel circuits.