A study on linear regression of cpi and miss ratios in hierarchy memory of nehalem systems

Abstract

Recently, with growing the gap between processors and memory speeds, parallel performance on chip multithread processors becomes more attractive for filling up this gap. It occurs the multithread scheduling on chip multithread processors to improve the performance. In this direction, calculating the Cycle per Instructions (CPI) and its relationship with miss ratios in hierarchy memory is important. To finding the correlation between CPI and miss ratios and footprints, it’s required to show linear relation between them at first. In this paper, linear regression between CPI and miss ratios has discussed in hierarchy memory including Translation Look-aside Buffer (TLB), first level of cache (L1), L2 and L3 on a Nehalem system. Intel-Vtune 2013 and SPEC-CPU 2000 benchmarks are used to measure the CPI and cache miss ratios.